A common goal in the integrated circuit (IC) industry is to continually strive to place more conductive circuitry into a smaller substrate surface area. As conductive elements are manufactured in closer proximity to one another to achieve this goal, cross-talk due to capacitive coupling between adjacent electrical devices increases greatly whereby device performance and product integrity is affected. To battle this increase in cross-talk and capacitive coupling between adjacent conductive members, the industry has begun to incorporate low-K dielectrics into integrated circuits (ICs) to provide improved electrical isolation between adjacent conductive regions of integrated circuit (IC) material.
When low-K dielectric material were first introduced in the IC industry, all low-K dielectric materials were blanketly deposited over the entire integrated circuit wafer in place of some conventional higher-K dielectric material. It was soon discovered that this blanket deposition of low-K material was not optimal. First, low-K dielectric materials, while providing improved electrical isolation between adjacent conductive elements, suffered from a lower mechanical strength than conventional higher-K dielectric materials. In addition, many low-K dielectric materials cannot survive high temperature processing, whereby the use of low-K dielectric materials significantly hinders subsequent IC thermal processing. Also, low-K dielectric materials have poor thermal conductivity. In fact, some low-K dielectric materials are five times less thermally conductive than conventional higher-K dielectrics such as silicon dioxide (SiO.sub.2). Therefore, when a low-K dielectric is blanketly deposited across the surface of an integrated circuit, this low-K dielectric layer tends to prevent heat dissipation from the products thereby resulting in elevated temperatures in active circuit regions of the integrated circuit (IC). In addition, many low-K dielectric materials suffer from a larger level of moisture absorption than other conventional dielectric materials. All of moisture absorption, out-gassing, low-K dielectric material flow over time, and geometrical changes in low-K dielectric shape during processing are serious concerns when using low-K material in the integrated circuit industry. In addition, many low-K dielectric materials have been documented as having poor adhesion characteristics and do not adequately adhere to other conventional integrated circuit (IC) materials such as conventional dielectrics and conventional metallic interconnect materials.
FIG. 1 illustrates a blanketly-deposited low-K dielectric embodiment which is known in the integrated circuit (IC) art. FIG. 1 illustrates three conductive metallic members 450, 451, and 452. These three conductive members 450-452 are encapsulated by a thin tetraethylorthosilicate (TEOS) layer 454. After formation of the layer 454, a blanket layer of low-K dielectric material 456 is deposited as illustrated in FIG. 1. After deposition of the layer 456, the blanket low-K dielectric layer 456 is followed with a second TEOS deposition step to form the TEOS layer 458 of FIG. 1. One or more contact openings 466 are etched through the layers 458, 456, and 454. The contact opening 466 is typically plugged with a conductive material such as tungsten (W). A second metallic layer is sputtered and patterned to form second-level conductive members 462 as illustrated in FIG. 1. As previously discussed, the layer 456 is a blanket layer of low-K dielectric material which suffers from lower mechanical strength, temperature limitations, lower thermal conductivity, moisture absorption, poor adhesion to other layers, and other disadvantages. Therefore, the blanket deposition of low-K dielectric materials, as illustrated in FIG. 1, is not optimal in the integrated circuit industry.
FIGS. 2-5 illustrate an alternate embodiment which has been used in the integrated circuit (IC) art to reduce the disadvantages discussed above with respect to blanketly-deposited low-K dielectric materials. The integrated circuit industry has recognized that the disadvantages/limitations of low-K dielectric materials can be lessened in impact if the use of low-K dielectric materials occurs in only select portions of an integrated circuit (IC) design. In other words, by forming low-K dielectric material in a non-blanketed manner only in critical areas of necessity, some of the effects of the low-K dielectric material's low mechanical strength, temperature limitations, lower thermal conductivity, moisture absorption, and poor adhesion, can either be avoided or reduced to within acceptable levels.
One method used to incorporate low-K dielectric material into a semiconductor structure in a manner that is non-blanket in configuration is illustrated in FIGS. 2-5. In FIG. 2, a base oxide layer 412 is provided. Conductive interconnects 414, 416, and 418 are formed overlying the oxide layer 412. At first, a blanket layer of low-K dielectric material 420 is deposited over the wafer as illustrated in FIG. 1. This layer 420 is then exposed to reactive ion etch (RIE) environment which etches the layer 420 into spacer formations 420 as illustrated in FIG. 3.
In FIG. 3, the low-K dielectric spacer structures 420 are not blanket in nature and therefore do not have as large of an adverse impact in integrated circuit mechanical strength, thermal conductivity, moisture absorption, and the like. In FIG. 3, the low-K dielectric and metal layers are then encapsulated via an oxide layer 422. In FIG. 3, conventional openings 426 are then etched through the dielectric layer 422 to form electrical contact openings which expose the conductive members 418, 416, and 414. Conductive plugs 430 and metal lines 432 and 434 are patterned in FIG. 5 to complete the electrical interconnection structures.
It is important to note that FIGS. 2-5 illustrate a conventional contact and interconnect process whereby metal lines are lithographically patterned and etched overlying existing oxide layers. This type of conventional interconnection formation is generally being phased out of the integrated circuit industry. A new process and structure, referred to as Damascene contacts or dual inlaid metal interconnects, are now being used in the IC industry. These dual inlaid contacts do not have exposed vertical sidewalls of conductive material such as the vertical sidewalls of the regions 414, 416, and 418 of FIG. 2. Since Damascene or dual inlaid structures do not have exposed metallic sidewalls, the formation of sidewall spacers laterally adjacent metal lines as illustrated in FIGS. 2-5 is not possible in Damascene or dual inlaid processing. Therefore, the process of FIGS. 2-5 cannot be utilized to form adequate low-K dielectric material in accordance with dual inlaid processing.
The need exists for a low-K dielectric process for Damascene contacts (dual inlaid contact) which selectively places low-K dielectric material where it is most needed whereby its selective placement will reduce some of the inherent weaknesses with low-K dielectric materials, such as the material's lower mechanical strength, its lower thermal conductivity, its moisture absorption, and the like.